DeSpice

A Python library for building SPICE circuits, generating netlists, running simulator backends, and reading results — with a PySpice-compatible API and a Rust core. The package is named pyspice-rs and imported as pyspice_rs.

Installation

python3 -m venv .venv
source .venv/bin/activate
pip install maturin numpy pytest
maturin develop

With Nix:

nix develop

Install at least one simulator to run analyses. Start with ngspice unless you need a specific backend. DeSpice supports ngspice, xyce, ltspice, spectre, and vacask; backend availability depends on what is installed locally.

First circuit

The recommended workflow separates the design under test (Subcircuit) from its stimulus and measurement harness (Testbench):

import pyspice_rs as ps
from pyspice_rs.unit import u_V, u_kOhm

# Design under test: a resistive divider with two ports
dut = ps.Subcircuit("divider", ["vin", "vout"])
dut.R(name="top", positive="vin", negative="vout", value=2 @ u_kOhm)
dut.R(name="bot", positive="vout", negative=dut.gnd, value=1 @ u_kOhm)

# Testbench: stimulus + backend + analysis
tb = ps.Testbench(dut)
tb.V(name="supply", positive="vin", negative=dut.gnd, value=10 @ u_V)
tb.with_backend("ngspice")

op = tb.operating_point()
print(op["vout"])   # ≈ 3.333 V

A flat Circuit works too, closer to classic PySpice:

circuit = ps.Circuit("voltage_divider")
circuit.V(name="in", positive="vin", negative=circuit.gnd, value=10 @ u_V)
circuit.R(name="top", positive="vin", negative="vout", value=2 @ u_kOhm)
circuit.R(name="bot", positive="vout", negative=circuit.gnd, value=1 @ u_kOhm)

print(circuit)  # netlist

sim = circuit.simulator(simulator="ngspice")
op = sim.operating_point()
print(op["vout"])

Highlights

• PySpice-compatible API — value @ u_kOhm units (Unicode aliases like u_µF, u_Ω included), familiar element and analysis names, .nodes/.branches on results.
• Backend hot-swap — one line (tb.with_backend("vacask")) switches simulators; netlists are generated per backend dialect.
• PDK hot-swap — ModelLibrary + tb.use_pdk() swap foundry models (sky130, gf180mcu, …) without touching topology.
• Full analysis set — OP, DC, AC, transient, noise, transfer function, sensitivity, pole-zero, distortion, PSS, S-parameters, harmonic balance, stability, Monte Carlo / sampling, FFT.
• Verilog-A and digital co-simulation — compile Verilog-A inline via OpenVAF/OSDI; bridge digital Verilog with XSPICE A-elements.
• Linting — validate netlists and check backend compatibility before simulating.

Testing your install

cargo test
maturin develop
python3 -m pytest -v